Revert "Revert "Merge branch 'master' of git.labs.intellij.net:idea/ultimate""

This reverts commit 3a2ad1f6c248ce02e860be14b796981de7ccfeee.

python/testData/codeInsight/controlflow/if.txt

@@ -4,12 +4,14 @@
 3(4,5) element: PyIfStatement
 4(6) element: PyStatementList. Condition: 1:true
 5(6) element: PyElsePart. Condition: 1:false
-6(7,8,9) element: PyIfStatement
-7(9) element: PyStatementList. Condition: 2:true
-8(9) element: PyIfPartIf. Condition: 3:true
-9(10,11,12) element: PyIfStatement
-10(14) element: PyStatementList. Condition: 4:true
-11(14) element: PyIfPartIf. Condition: 5:true
-12(13) element: PyElsePart. Condition: 5:false
-13(14) element: PyExpressionStatement
-14() element: null
+6(7,8) element: PyIfStatement
+7(10) element: PyStatementList. Condition: 2:true
+8(9,10) element: PyIfPartElif. Condition: 2:false
+9(10) element: PyIfPartElif. Condition: 3:true
+10(11,12) element: PyIfStatement
+11(16) element: PyStatementList. Condition: 4:true
+12(13,14) element: PyIfPartElif. Condition: 4:false
+13(16) element: PyIfPartElif. Condition: 5:true
+14(15) element: PyElsePart. Condition: 5:false
+15(16) element: PyExpressionStatement
+16() element: null

python/testData/codeInsight/controlflow/manyifs.py

@@ -0,0 +1,13 @@
+var = 1
+if a == b:
+    var = 2
+elif aa == bb:
+    bbb = same_changet_expression
+
+    if bbb:
+        var = 3 # <--- this highlight bug (unused variable)
+
+else:
+    var = 4
+
+return {'variable': var}

python/testData/codeInsight/controlflow/manyifs.txt

@@ -0,0 +1,27 @@
+0(1) element: null
+1(2) element: PyAssignmentStatement
+2(3) WRITE ACCESS: var
+3(4) element: PyIfStatement
+4(5) READ ACCESS: a
+5(6,9) READ ACCESS: b
+6(7) element: PyStatementList. Condition: a == b:true
+7(8) element: PyAssignmentStatement
+8(24) WRITE ACCESS: var
+9(10,21) element: PyIfPartElif. Condition: a == b:false
+10(11) READ ACCESS: aa
+11(12) READ ACCESS: bb
+12(13) element: PyIfPartElif. Condition: aa == bb:true
+13(14) element: PyAssignmentStatement
+14(15) READ ACCESS: same_changet_expression
+15(16) WRITE ACCESS: bbb
+16(17) element: PyIfStatement
+17(18,24) READ ACCESS: bbb
+18(19) element: PyStatementList. Condition: bbb:true
+19(20) element: PyAssignmentStatement
+20(24) WRITE ACCESS: var
+21(22) element: PyElsePart. Condition: aa == bb:false
+22(23) element: PyAssignmentStatement
+23(24) WRITE ACCESS: var
+24(25) element: PyReturnStatement
+25(26) READ ACCESS: var
+26() element: null